EH2525TTS-66.666M
EH25 25
Series
RoHS Compliant (Pb-free) 5.0V 4 Pad 5mm x 7mm
Ceramic SMD HCMOS/TTL High Frequency Oscillator
Frequency Tolerance/Stability
±25ppm Maximum
Operating Temperature Range
0°C to +70°C
RoHS
Pb
Nominal Frequency
66.666MHz
T TS -66.666M
Pin 1 Connection
Tri-State (High Impedance)
Duty Cycle
50 ±5(%)
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
66.666MHz
±25ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the
Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at 25°C,
Shock, and Vibration)
±5ppm/year Maximum
0°C to +70°C
5.0Vdc ±10%
50mA Maximum (No Load)
2.4Vdc Minimum with TTL Load, Vdd-0.4Vdc Minimum with HCMOS Load (IOH= -16mA)
0.4Vdc Maximum with TTL Load, 0.5Vdc Maximum with HCMOS Load (IOH= +16mA)
6nSec Maximum (Measured at 0.8Vdc to 2.0Vdc with TTL Load; Measured at 20% to 80% of waveform
with HCMOS Load)
50 ±5(%) (Measured at 50% of waveform with TTL Load or with HCMOS Load)
10TTL Load or 50pF HCMOS Load Maximum
CMOS
Tri-State (High Impedance)
+2.2Vdc Minimum to enable output, +0.8Vdc Maximum to disable output (High Impedance), No Connect to
enable output.
±250pSec Maximum, ±100pSec Typical
±50pSec Maximum, ±30pSec Typical
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Pin 1 Connection
Tri-State Input Voltage (Vih and Vil)
Absolute Clock Jitter
One Sigma Clock Period Jitter
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Moisture Sensitivity
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 3015, Class 1, HBM: 1500V
MIL-STD-883, Method 1014, Condition A
UL94-V0
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 2/17/2010 | Page 1 of 6
EH2525TTS-66.666M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
CONNECTION
Tri-State
Ground
Output
Supply Voltage
7.00
±0.15
3
5.00
±0.15
MARKING
ORIENTATION
2
1.4 ±0.1
5.08
±0.15
4
2.20
±0.15
1
1.4 ±0.2
3.68
±0.15
1
2
3
4
LINE MARKING
1
2
3
ECLIPTEK
66.666M
PXXYZZ
P=Configuration Designator
XX=Ecliptek Manufacturing
Code
Y=Last Digit of the Year
ZZ=Week of the Year
1.60 ±0.20
Suggested Solder Pad Layout
All Dimensions in Millimeters
2.0 (X4)
2.2 (X4)
2.88
Solder Land
(X4)
1.81
All Tolerances are ±0.1
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 2/17/2010 | Page 2 of 6
EH2525TTS-66.666M
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
80% or 2.0V
DC
50% or 1.4V
DC
20% or 0.8V
DC
V
OL
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
Test Circuit for TTL Output
Output Load
Drive Capability
10TTL
5TTL
2TTL
10LSTTL
1TTL
R
L
Value
(Ohms)
390
780
1100
2000
2200
C
L
Value
(pF)
15
15
6
15
3
Oscilloscope
Frequency
Counter
Table 1: R
L
Resistance Value and C
L
Capacitance
Value Vs. Output Load Drive Capability
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
R
L
(Note 4)
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
+
0.01µF
(Note 1)
0.1µF
(Note 1)
C
L
(Note 3)
Power
Supply
_
Ground
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
Note 4: Resistance value R
L
is shown in Table 1. See applicable specification sheet for 'Load Drive Capability'.
Note 5: All diodes are MMBD7000, MMBD914, or equivalent.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 2/17/2010 | Page 3 of 6
EH2525TTS-66.666M
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 2/17/2010 | Page 4 of 6
EH2525TTS-66.666M
Recommended Solder Reflow Methods
T
P
Critical Zone
T
L
to T
P
Ramp-up
Ramp-down
Temperature (T)
T
L
T
S
Max
T
S
Min
t
S
Preheat
t 25°C to Peak
t
L
t
P
Time (t)
High Temperature Infrared/Convection
T
S
MAX to T
L
(Ramp-up Rate)
Preheat
- Temperature Minimum (T
S
MIN)
- Temperature Typical (T
S
TYP)
- Temperature Maximum (T
S
MAX)
- Time (t
S
MIN)
Ramp-up Rate (T
L
to T
P
)
Time Maintained Above:
- Temperature (T
L
)
- Time (t
L
)
Peak Temperature (T
P
)
Target Peak Temperature (T
P
Target)
Time within 5°C of actual peak (t
p
)
Ramp-down Rate
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
Additional Notes
3°C/second Maximum
150°C
175°C
200°C
60 - 180 Seconds
3°C/second Maximum
217°C
60 - 150 Seconds
260°C Maximum for 10 Seconds Maximum
250°C +0/-5°C
20 - 40 seconds
6°C/second Maximum
8 minutes Maximum
Level 1
Temperatures shown are applied to body of device.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 2/17/2010 | Page 5 of 6
